As semiconductor technologies evolve, integrated circuits (IC) have migrated to small feature sizes, such as 65 nanometers, 45 nanometers, 32 nanometers and below. Semiconductor technologies with small feature sizes lead to more interactions between semiconductor fabrication and design. For example, the impact of parasitic effects will become more important for devices with small feature sizes. A variety of simulation and optimization procedures may be performed by IC designers to ensure the devices with small feature sizes meet the performance index to which they are specified.
One parasitic effect is parasitic elements derived from electrical characteristics of interconnected conductors of an IC. As known in the art, in a front-end-of-line (FEOL) process, an active layer is formed in a substrate. Once the active layer has been created, in a back-end-of-line (BEOL) process, a plurality of interconnect layers are formed on top of the active layer. In each interconnect layer, a metal layer is deposited first, then patterned so that various metal conductors are created. The metal conductors in different layers are interconnected by vias. As metal conductors are located in close proximity to each other, parasitic capacitances are formed between any two of them. In addition, a parasitic capacitance is also formed between a metal interconnect and ground.
In order to design high performance integrated circuits, the parasitic capacitance, inductance and resistance of interconnect conductors may be modeled so that some critical issues such as timing, noise and reliability can be accurately assessed. Various Electronic Design Automation (EDA) tools may be used to extract parasitic capacitance and resistance. For example, an EDA tool such as RAPHAEL from SYNOPSYS may first receive a SPICE model file from an IC foundry. Then, the EDA tool calculates the parasitic capacitance values related to each interconnect conductor by means of a field solver. The outcome of the field solver is saved as a resistance-capacitance (RC) technology file.
The generation of RC technology files is timing consuming. In addition, for an IC foundry, different clients may have slightly different interconnect structures. However, an IC foundry is required to dedicate one RC technology file for each interconnect structure despite that the difference between a variety of interconnect structures are minimal. In consideration of the large number of clients an IC foundry may have, the generation of RC technology files in a limited period of time is a challengeable job.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.